24 search results - page 4 / 5 » A loop accelerator for low power embedded VLIW processors |
DAC
2002
ACM
14 years 6 months ago
2002
ACM
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Modern digital signal processing applications have an increasing demand for computational power while needing to preserve low power dissipation and high flexibility. For many appl...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
CODES
2009
IEEE
13 years 6 months ago
2009
IEEE
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...