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» A low power architecture for embedded perception
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GLVLSI
2010
IEEE
187views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Write activity reduction on flash main memory via smart victim cache
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
Liang Shi, Chun Jason Xue, Jingtong Hu, Wei-Che Ts...
DAC
2010
ACM
13 years 8 months ago
A probabilistic and energy-efficient scheduling approach for online application in real-time systems
This work considers the problem of minimizing the power consumption for real-time scheduling on processors with discrete operating modes. We provide a model for determining the ex...
Thorsten Zitterell, Christoph Scholl
DAC
2008
ACM
14 years 6 months ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
AES
2005
Springer
137views Cryptology» more  AES 2005»
13 years 5 months ago
Design of a multimedia processor based on metrics computation
Media-processing applications, such as signal processing, 2D and 3D graphics rendering, and image compression, are the dominant workloads in many embedded systems today. The real-...
Nader Ben Amor, Yannick Le Moullec, Jean-Philippe ...
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
13 years 11 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt