21 search results - page 2 / 5 » A low voltage CMOS multiplier for high frequency equalizatio... |
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
ESSCIRC
2011
12 years 5 months ago
2011
— Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations wi...
ISLPED
2010
ACM
13 years 5 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— A low energy modulo-multiplier is proposed for elliptic curve cryptography (ECC) processor, especially for authentication in mobile device or key encryption in embedded health-...
ENGL
2007
13 years 5 months ago
2007
—A 2.5V high precision BiCMOS bandgap reference with supply voltage range of 6V to 18V was proposed and realized. It could be applied to lots of Power Management ICs (Intergrated...