2 search results - page 1 / 1 » A low-area, low-power programmable frequency multiplier for ... |
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
A low-power output feedback controlled frequency synthesizer. Our proposed circuit can be used for low-power multiplier is proposed for Delay Locked Loop (DLL) based application an...