4 search results - page 1 / 1 » A low-overhead fault tolerance scheme for TSV-based 3D netwo... |
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
— Three-dimensional die stacking integration provides the ability to stack multiple layers of processed silicon with a large number of vertical interconnects. Through Silicon Via...
TCAD
2010
12 years 11 months ago
2010
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
SBCCI
2005
ACM
13 years 10 months ago
2005
ACM
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
LCTRTS
2010
Springer
13 years 2 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...