13 search results - page 2 / 3 » A low-power SRAM using bit-line charge-recycling technique |
VTS
2005
IEEE
13 years 10 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
AHS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we present a low power implementation of H.264 adaptive deblocking filter (DBF) algorithm on ARM Versatile / PB926EJ-S Development Board. The DBF hardware is implem...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
∗ Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, a...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...