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2002
IEEE

Architecture and Design of a High Performance SRAM for SOC Design

10 years 11 months ago
Architecture and Design of a High Performance SRAM for SOC Design
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropriate circuit partitioning, transistor sizing, choice of a suitable Sense Amplifier, a good resetting technique and judicial use of dual Vth transistors we have achieved a high speed memory without dissipating too much power.
Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka P
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2002
Where VLSID
Authors Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout
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