9 search results - page 1 / 2 » A low-power VLSI architecture for turbo decoding |
ISLPED
1998
ACM
13 years 9 months ago
1998
ACM
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
ICC
2007
IEEE
13 years 11 months ago
2007
IEEE
— We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value–reuse property of offs...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...