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DAC
2002
ACM
14 years 6 months ago
DRG-cache: a data retention gated-ground cache for low power
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
Amit Agarwal, Hai Li, Kaushik Roy
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 1 days ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
VLSID
2007
IEEE
130views VLSI» more  VLSID 2007»
14 years 6 months ago
Impact of NBTI on FPGAs
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
Krishnan Ramakrishnan, S. Suresh, Narayanan Vijayk...
IFM
2010
Springer
183views Formal Methods» more  IFM 2010»
13 years 3 months ago
Certified Absence of Dangling Pointers in a Language with Explicit Deallocation
Safe is a first-order eager functional language with facilities for programmer controlled destruction and copying of data structures. It provides also regions, i.e. disjoint parts...
Javier de Dios, Manuel Montenegro, Ricardo Pe&ntil...
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 8 days ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...