Sciweavers

36 search results - page 2 / 8
» A new efficient and flexible algorithm for the design of tes...
Sort
View
ARC
2006
Springer
124views Hardware» more  ARC 2006»
13 years 9 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
13 years 9 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
EVOW
2001
Springer
13 years 10 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
GECCO
2004
Springer
166views Optimization» more  GECCO 2004»
13 years 11 months ago
An Effective Chromosome Representation for Evolving Flexible Job Shop Schedules
As the Flexible Job Shop Scheduling Problem (or FJSP) is strongly NP-hard, using an evolutionary approach to find near-optimal solutions requires effective chromosome representatio...
Joc Cing Tay, Djoko Wibowo
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
13 years 11 months ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek