47 search results - page 2 / 10 » A performance counter architecture for computing accurate CP... |
ICS
2007
Tsinghua U.
13 years 11 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
We present our practical experience in the modeling and integration of cycle/phase-accurate instruction set architecture (ISA) models of digital signal processors (DSPs) with othe...
ISCA
2009
IEEE
13 years 11 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
DAC
2000
ACM
13 years 9 months ago
2000
ACM
Abstract: This paper presents a new statistical methodology to simulate the effect of both inter-die and intra-die variation on the electrical performance of analog integrated circ...
VLSID
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...