23 search results - page 3 / 5 » A power and temperature aware DRAM architecture |
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
DAC
2011
ACM
12 years 4 months ago
2011
ACM
We study the problem on how to maximize the throughput for a periodic real-time system under the given peak temperature constraint. We assume that different tasks in our system ma...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) ...
VLSID
2007
IEEE
14 years 5 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
IJES
2007
13 years 4 months ago
2007
: The power density in high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating ‘hot spotsâ€...