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» A programmable built-in self-test core for embedded memories
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TOG
2012
230views Communications» more  TOG 2012»
11 years 7 months ago
Decoupling algorithms from schedules for easy optimization of image processing pipelines
Using existing programming tools, writing high-performance image processing code requires sacrificing readability, portability, and modularity. We argue that this is a consequenc...
Jonathan Ragan-Kelley, Andrew Adams, Sylvain Paris...
FPL
2006
Springer
127views Hardware» more  FPL 2006»
13 years 9 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
ARCS
2004
Springer
13 years 9 months ago
Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing
: This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamical...
Walter Stechele, Stephan Herrmann, Andreas Herkers...
NOCS
2009
IEEE
14 years 22 hour ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas