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TWC
2010
13 years 9 days ago
A Reduced-Complexity PTS-Based PAPR Reduction Scheme for OFDM Systems
In this paper, a reduced-complexity partial transmit sequences (PTS) scheme is proposed to resolve the intrinsic high peak-to-average power ratio (PAPR) problem of orthogonal frequ...
Sheng-Ju Ku, Chin-Liang Wang, Chiuan-Hsu Chen
ICCD
2002
IEEE
93views Hardware» more  ICCD 2002»
14 years 2 months ago
Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
David Duarte, Narayanan Vijaykrishnan, Mary Jane I...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 3 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
DAC
2004
ACM
14 years 6 months ago
Leakage-and crosstalk-aware bus encoding for total power reduction
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
Harmander Deogun, Rajeev R. Rao, Dennis Sylvester,...
DFT
2002
IEEE
117views VLSI» more  DFT 2002»
13 years 10 months ago
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
Ozgur Sinanoglu, Alex Orailoglu