Sciweavers

33 search results - page 2 / 7
» A strategy for MINLP synthesis of flexible and operable proc...
Sort
View
CASES
2000
ACM
13 years 9 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
FPGA
2008
ACM
168views FPGA» more  FPGA 2008»
13 years 6 months ago
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs
The Field Programmable Counter Array (FPCA) was introduced to improve FPGA performance for arithmetic circuits. An FPCA is a reconfigurable IP core that can be integrated into an ...
Alessandro Cevrero, Panagiotis Athanasopoulos, Had...
DATE
2003
IEEE
137views Hardware» more  DATE 2003»
13 years 10 months ago
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs
We present two novel strategies to increase the scope for application of speculative code motions: (1) Adding scheduling steps dynamically during scheduling to conditional branche...
Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexa...
ICDE
2007
IEEE
221views Database» more  ICDE 2007»
13 years 11 months ago
Flexible Multi-Threaded Scheduling for Continuous Queries over Data Streams
A variety of real-world applications share the property that data arrives in form of transient streams. Data stream management systems (DSMS) provide convenient solutions to the p...
Michael Cammert, Christoph Heinz, Jürgen Kr&a...
ESWA
2008
162views more  ESWA 2008»
13 years 5 months ago
Proportionate flexible flow shop scheduling via a hybrid constructive genetic algorithm
The proportionate flow shop (PFS) is considered as a unique case of the flow shop problem in which the processing times of the operations belonging to the same job are equal. A pr...
Der-Fang Shiau, Shu-Chen Cheng, Yueh-Min Huang