11 search results - page 2 / 3 » A systematic approach to modeling and analysis of transient ... |
DDECS
2007
IEEE
13 years 11 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
VLSID
1997
IEEE
13 years 9 months ago
1997
IEEE
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
AB
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. In 1973 R. Thomas introduced a logical approach to modeling and analysis of bioregulatory networks. Given a set of Boolean functions describing the regulatory interaction...
VTS
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...