169 search results - page 1 / 34 » A timing analysis algorithm for circuits with level-sensitiv... |
ASPDAC
2010
ACM
13 years 3 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...