169 search results - page 3 / 34 » A timing analysis algorithm for circuits with level-sensitiv... |
ICCD
2008
IEEE
14 years 3 months ago
2008
IEEE
- This paper performs analysis and design of latches and flip-flops while considering the effect of event upsets caused by energetic particle hits. First it is shown that the conve...
GLVLSI
2008
IEEE
14 years 18 days ago
2008
IEEE
Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for emp...
IJFCS
1998
13 years 5 months ago
1998
Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
DAC
2003
ACM
14 years 7 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...