Sciweavers

48 search results - page 2 / 10
» AHIR: A Hardware Intermediate Representation for Hardware Ge...
Sort
View
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
12 years 9 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 7 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
ERSA
2008
145views Hardware» more  ERSA 2008»
13 years 7 months ago
Multicore Devices: A New Generation of Reconfigurable Architectures
For two decades, reconfigurable computing systems have provided an attractive alternative to fixed hardware solutions. Reconfigurable computing systems have demonstrated the low c...
Steven A. Guccione
DATE
2009
IEEE
176views Hardware» more  DATE 2009»
14 years 8 days ago
Automated synthesis of streaming C applications to process networks in hardware
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
Sven van Haastregt, Bart Kienhuis