13 search results - page 2 / 3 » Accelerating architectural exploration using canonical instr... |
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we show a novel approach to accelerate loops by tightly coupling a coprocessor to an ASIP. Latency hiding is used to exploit the parallelism available in this archi...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
18
Voted
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
DAC
2004
ACM
13 years 10 months ago
2004
ACM
Silicon compilers are often used in conjunction with Field Programmable Gate Arrays (FPGAs) to deliver flexibility, fast prototyping, and accelerated time-to-market. Many of these...
MOBILIGHT
2010
13 years 2 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...