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TC
2010
12 years 11 months ago
A Counter Architecture for Online DVFS Profitability Estimation
Dynamic voltage and frequency scaling (DVFS) is a well known and effective technique for reducing power consumption in modern microprocessors. An important concern though is to est...
Stijn Eyerman, Lieven Eeckhout
ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
13 years 11 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 8 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...