75 search results - page 3 / 15 » Accurate Area, Time and Power Models for FPGA-Based Implemen... |
CODES
2004
IEEE
13 years 9 months ago
2004
IEEE
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hard...
ICPPW
2008
IEEE
13 years 11 months ago
2008
IEEE
Power minimization is a serious issue in wireless sensor networks to extend the lifetime and minimize costs. However, in order to gain an accurate understanding of issues regardin...
HICSS
2002
IEEE
13 years 10 months ago
2002
IEEE
We analyze alternative market designs for a multisettlement system for electricity in which the resolution of the transmission network model is increased as time approaches real-t...