51 search results - page 3 / 11 » Accurate timing analysis by modeling caches, speculation and... |
ICCD
2007
IEEE
13 years 10 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
BIS
2009
13 years 7 months ago
2009
Abstract. The quality of today's digital maps is very high. This allows for new functionality as illustrated by modern car navigation systems (e.g., TomTom, Garmin, etc.), Goo...
RTSS
2006
IEEE
14 years 5 days ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
ICCAD
2007
IEEE
14 years 3 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
RTS
2006
13 years 6 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...