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» Active leakage power optimization for FPGAs
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FPGA
2004
ACM
136views FPGA» more  FPGA 2004»
13 years 10 months ago
Active leakage power optimization for FPGAs
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
Jason Helge Anderson, Farid N. Najm, Tim Tuan
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
13 years 10 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
DATE
2005
IEEE
169views Hardware» more  DATE 2005»
13 years 10 months ago
Activity Packing in FPGAs for Leakage Power Reduction
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a ...
Hassan Hassan, Mohab Anis, Antoine El Daher, Moham...
APCCAS
2006
IEEE
271views Hardware» more  APCCAS 2006»
13 years 10 months ago
Leakage Optimized DECAP Design for FPGAs
— On-chip decoupling capacitors (Decaps) are widely used to mitigate on-chip power supply noise. At and below 100nm on-chip decaps face leakage and area overhead problems associa...
Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, ...
ISCAS
2007
IEEE
126views Hardware» more  ISCAS 2007»
13 years 11 months ago
Optimal Body Biasing for Minimum Leakage Power in Standby Mode
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
Kyung Ki Kim, Yong-Bin Kim