37 search results - page 2 / 8 » Activity Estimation for Field-Programmable Gate Arrays |
ISCAS
2008
IEEE
14 years 4 days ago
2008
IEEE
— This paper presents models for estimating the transition activity of signals at the output of adders in Field Programmable Gate Arrays (FPGAs), given only word-level measures o...
ISCAS
2002
IEEE
13 years 10 months ago
2002
IEEE
The evaluation of power consumption in complex digital systems is a hard task that normally requires long simulation time and complicated models. In this work, we obtain power con...
IPPS
1999
IEEE
13 years 10 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
DATE
2002
IEEE
13 years 10 months ago
2002
IEEE
We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic de...