38 search results - page 1 / 8 » Activity Packing in FPGAs for Leakage Power Reduction |
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a ...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A negative effect of ever-shrinking supply and threshold voltages is the larger percentage of total power consumption that comes from leakage current. Several techniques have been...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...