35 search results - page 3 / 7 » Adaptive Channel Buffers in On-Chip Interconnection Networks... |
ICS
2009
Tsinghua U.
13 years 10 months ago
2009
Tsinghua U.
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
NOCS
2008
IEEE
14 years 1 days ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
GLOBECOM
2008
IEEE
14 years 4 days ago
2008
IEEE
— We present a crosslayer framework for optimizing the performance of wireless networks as measured by applications or upper layer protocols. The approach combines adaptive modul...