Sciweavers

691 search results - page 1 / 139
» Adaptive Power Management for the On-Chip Communication Netw...
Sort
View
DSD
2006
IEEE
120views Hardware» more  DSD 2006»
13 years 10 months ago
Adaptive Power Management for the On-Chip Communication Network
— An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this regi...
Guang Liang, Axel Jantsch
TC
2008
13 years 4 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
13 years 9 months ago
An Adaptive Low-Power Transmission Scheme for On-Chip Networks
Paolo Ienne, Patrick Thiran, Giovanni De Micheli, ...
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
13 years 10 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
ICPP
2005
IEEE
13 years 10 months ago
Peak Power Control for a QoS Capable On-Chip Network
In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-c...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum