Sciweavers

486 search results - page 4 / 98
» Adaptive estimation and prediction of power and performance ...
Sort
View
LCN
2005
IEEE
13 years 11 months ago
Implementation and Performance Analysis of a Packet Scheduler on a Programmable Network Processor
— The problem of achieving fairness in the allocation of the bandwidth resource on a link shared by multiple flows of traffic has been extensively researched over the last deca...
Fariza Sabrina, Salil S. Kanhere, Sanjay Jha
ICRA
2005
IEEE
257views Robotics» more  ICRA 2005»
13 years 11 months ago
Nonlinear Performance Limits for High Energy Density Piezoelectric Bending Actuators
Abstract— To keep pace with recent advances in microrobotic structures demands actuator technologies which can deliver high power and precise motion. For electroactive material b...
Robert J. Wood, Erik Steltz, Ronald S. Fearing
ISLPED
2003
ACM
100views Hardware» more  ISLPED 2003»
13 years 10 months ago
Checkpointing alternatives for high performance, power-aware processors
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
Andreas Moshovos
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
14 years 5 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
HPCA
2009
IEEE
14 years 6 months ago
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics
The shrinking processor feature size, lower threshold voltage and increasing clock frequency make modern processors highly vulnerable to transient faults. Architectural Vulnerabil...
Lide Duan, Bin Li, Lu Peng