114 search results - page 4 / 23 » Address Register Assignment for Reducing Code Size |
IPPS
1996
IEEE
13 years 9 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
An important class of problems used widely in both the embedded systems and scientific domains perform memory intensive computations on large data sets. These data sets get to be ...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
PLDI
2003
ACM
13 years 10 months ago
2003
ACM
We compile Nova, a new language designed for writing network processing applications, using a back end based on integer-linear programming (ILP) for register allocation, optimal b...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
An Application Specific Instruction Set Processor (ASIP) exploits special characteristics of the given application(s) to meet the desired performance, cost and power requirements....