114 search results - page 5 / 23 » Address Register Assignment for Reducing Code Size |
LCTRTS
2010
Springer
13 years 7 months ago
2010
Springer
DSP processors usually provide dedicated address generation units (AGUs) to assist address computation. By carefully allocating variables in the memory, DSP compilers take advanta...
CC
2006
Springer
13 years 9 months ago
2006
Springer
Commonly-used memory units enable a processor to load and store multiple registers in one instruction. We showed in 2003 how to extend gcc with a stack-location-allocation (SLA) ph...
MICRO
1997
IEEE
13 years 10 months ago
1997
IEEE
The multicluster architecture that we introduce offers a decentralized, dynamically-scheduled architecture, in which the register files, dispatch queue, and functional units of t...
WMPI
2004
ACM
13 years 11 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
EMSOFT
2004
Springer
13 years 11 months ago
2004
Springer
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both hig...