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» Algorithm and Hardware Support for Branch Anticipation
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GLVLSI
1997
IEEE
110views VLSI» more  GLVLSI 1997»
13 years 9 months ago
Algorithm and Hardware Support for Branch Anticipation
Multi-dimensional systems containing nested loops are widely used to model scientific applications such as image processing, geophysical signal processing and fluid dynamics. Ho...
Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Pa...
MICRO
2010
IEEE
149views Hardware» more  MICRO 2010»
13 years 2 months ago
Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels
Wide Single Instruction, Multiple Thread (SIMT) architectures often require a static allocation of thread groups that are executed in lockstep throughout the entire application ker...
Michael Steffen, Joseph Zambreno
CCO
2001
Springer
161views Combinatorics» more  CCO 2001»
13 years 9 months ago
Branch, Cut, and Price: Sequential and Parallel
Branch, cut, and price (BCP) is an LP-based branch and bound technique for solving large-scale discrete optimization problems (DOPs). In BCP, both cuts and variables can be generat...
Laszlo Ladányi, Ted K. Ralphs, Leslie E. Tr...
TOG
2002
112views more  TOG 2002»
13 years 4 months ago
Ray tracing on programmable graphics hardware
Recently a breakthrough has occurred in graphics hardware: fixed function pipelines have been replaced with programmable vertex and fragment processors. In the near future, the gr...
Timothy J. Purcell, Ian Buck, William R. Mark, Pat...
ICPP
1999
IEEE
13 years 9 months ago
Optimization of Instruction Fetch for Decision Support Workloads
Instruction fetch bandwidth is feared to be a major limiting factor to the performance of future wide-issue aggressive superscalars. In this paper, we focus on Database applicatio...
Alex Ramírez, Josep-Lluis Larriba-Pey, Carl...