3 search results - page 1 / 1 » Alleviating the Data Memory Bandwidth Bottleneck in Coarse-G... |
ASAP
2005
IEEE
13 years 10 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
IPPS
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a compiler methodology for memoryaware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications’ p...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...