23 search results - page 2 / 5 » An ASIC perspective on FPGA optimizations |
CDES
2006
13 years 6 months ago
2006
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
ICCAD
2003
IEEE
14 years 2 months ago
2003
IEEE
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Digital Down Conversion (DDC) is an algorithm, used to lower the amount of samples per second by selecting a limited frequency band out of a stream of samples. A possible DDC algo...