5 search results - page 1 / 1 » An Accelerated Datapath Width Optimization Scheme for Area R... |
ISSS
2002
IEEE
13 years 9 months ago
2002
IEEE
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
A high-performance data-path to implement DSP kernels is proposed in this paper. The data-path is based on a flexible, universal, and regular component to optimally exploiting both...
CGO
2007
IEEE
13 years 11 months ago
2007
IEEE
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
VLSISP
2008
13 years 4 months ago
2008
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...