26 search results - page 3 / 6 » An Accurate and Efficient Time-Division Parallelization of C... |
DAC
2004
ACM
13 years 10 months ago
2004
ACM
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
VLSID
2003
IEEE
2003
IEEE
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
14 years 5 months ago
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
EUROPAR
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. Shared last level cache is crucial to performance. However, multithread program model incurs serious contention in shared cache. In this paper, to reduce average cache ac...
CF
2008
ACM
13 years 7 months ago
2008
ACM
PRAM (Parallel Random Access Model) has been widely regarded a desirable parallel machine model for many years, but it is also believed to be "impossible in reality." As...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...