166 search results - page 5 / 34 » An Adaptive Issue Queue for Reduced Power at High Performanc... |
HPCA
2007
IEEE
14 years 6 months ago
2007
IEEE
3D integration technology greatly increases transistor density while providing faster on-chip communication. 3D implementations of processors can simultaneously provide both laten...
CCGRID
2010
IEEE
13 years 4 months ago
2010
IEEE
—While computing speed continues increasing rapidly, data-access technology is lagging behind. Data-access delay, not the processor speed, becomes the leading performance bottlen...
TC
2008
13 years 5 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
IWCMC
2006
ACM
13 years 11 months ago
2006
ACM
Adaptively adjusting transmission rate and power to concurrently enhance goodput and save energy is an important issue in the wireless local area network (WLAN). However, goodput ...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...