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» An Architectural Power Estimator for Analog-to-Digital Conve...
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DAC
2002
ACM
14 years 5 months ago
Petri net modeling of gate and interconnect delays for power estimation
In this paper, a new type of Petri net called Hierarchical Colored Hardware Petri net, to model real-delay switching activity for power estimation is proposed. The logic circuit i...
Ashok K. Murugavel, N. Ranganathan
ICC
2007
IEEE
143views Communications» more  ICC 2007»
13 years 11 months ago
Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications
Abstract— Ultra-wideband (UWB) impulse radio is a promising technique for low-power bio-medical communication systems. While a range of analog and digital UWB architectures exist...
Andrew Fort, Mike Chen, Robert W. Brodersen, Claud...