133 search results - page 2 / 27 » An Architecture for a Hardware Implementation of the OSPF Pr... |
WISA
2007
Springer
13 years 11 months ago
2007
Springer
Abstract. The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have be...
DELTA
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a hardware architecture for layer 2 Multi Protocol Label Switching (MPLS). MPLS is a protocol framework used primarily to prioritize internet traffic and impro...
IPPS
2007
IEEE
13 years 12 months ago
2007
IEEE
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
FPL
1997
Springer
13 years 9 months ago
1997
Springer
Protocol Boosters are functional elements, inserted anddeleted fromnetwork protocol stacks on an as-neededbasis. The Protocol Booster design methodology attempts to improve end-to-...
IPPS
2003
IEEE
13 years 11 months ago
2003
IEEE
This paper describes a hardware architecture for modular multiplication operation which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptogra...