39 search results - page 1 / 8 » An Efficient Hardware Architecture without Line Memories for... |
ACIVS
2008
Springer
13 years 7 months ago
2008
Springer
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
ICASSP
2011
IEEE
12 years 8 months ago
2011
IEEE
X-ray computed tomography (CT) images could be improved using iterative image reconstruction if the 3D conebeam forward- and back-projection computations can be accelerated signif...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
Automatic vectorization of programs for partitioned-ALU SIMD (Single Instruction Multiple Data) processors has been difficult because of not only data dependency issues but also n...
CONCURRENCY
2004
2004
User transparency: a fully sequential programming model for efficient data parallel image processing
13 years 4 months ago
Although many image processing applications are ideally suited for parallel implementation, most researchers in imaging do not benefit from high performance computing on a daily b...