4 search results - page 1 / 1 » An Efficient Technique for Leakage Current Estimation in Sub... |
VLSID
2007
IEEE
14 years 4 months ago
2007
IEEE
With scaling of CMOS technologies, sub-threshold, gate and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together they account for more than 2...
VLSID
2006
IEEE
14 years 4 months ago
2006
IEEE
For a nanoCMOS of sub-65nm technology, where the gate oxide (SiO2) thickness is very low, the gate leakage is one of the major components of power dissipation. In this paper, we pr...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
– In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circu...
TVLSI
2008
13 years 4 months ago
2008
With continued scaling into the sub-90nm regime, the role of process, voltage and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. T...