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» An Embedded Core for Sub-Picosecond Timing Measurements
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ITC
2002
IEEE
99views Hardware» more  ITC 2002»
13 years 9 months ago
An Embedded Core for Sub-Picosecond Timing Measurements
The continued market demand for GHz processors and high-capacity communication systems results in an increasing number of low-cost high volume ICs with multi-GHz clocks and/or mul...
Sassan Tabatabaei, André Ivanov
CSREAESA
2006
13 years 6 months ago
Fast Run-Time Power Monitoring Methodology for Embedded Systems
Traditional simulation-based energy estimation is not practical because the simulation time has increased from minutes and hours and weeks. Therefore, simulation assisted by speci...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
EVOW
2008
Springer
13 years 6 months ago
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodolo...
Danilo Ravotto, Ernesto Sánchez, Massimilia...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
13 years 9 months ago
Security-Driven Exploration of Cryptography in DSP Cores
With the popularity of wireless communication devices a new important dimension of embedded systems design has arisen, that of security. This paper presents for the first time des...
Catherine H. Gebotys
CODES
2005
IEEE
13 years 10 months ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...