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» An Enhanced Multilevel Algorithm for Circuit Placement
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ICCAD
2005
IEEE
118views Hardware» more  ICCAD 2005»
14 years 2 months ago
Thermal via planning for 3-D ICs
Heat dissipation is one of the most serious challenges in 3D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias....
Jason Cong, Yan Zhang
ICCAD
2003
IEEE
148views Hardware» more  ICCAD 2003»
14 years 2 months ago
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
In this paper we present a family of multi-objective hypergraph partitioning algorithms based on the multilevel paradigm, which are capable of producing solutions in which both th...
Navaratnasothie Selvakkumaran, George Karypis
TCAD
2008
81views more  TCAD 2008»
13 years 5 months ago
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
Stephen Plaza, Igor L. Markov, Valeria Bertacco
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
13 years 11 months ago
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
Due to the rapid development of manufacturing process technology and tight marketing schedule, the chip design and manufacturing always work toward an integrated solution to achie...
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
DAC
1996
ACM
13 years 10 months ago
A Boolean Approach to Performance-Directed Technology Mapping for LUT-Based FPGA Designs
Abstract -- This paper presents a novel, Boolean approach to LUTbased FPGA technology mapping targeting high performance. As the core of the approach, we have developed a powerful ...
Christian Legl, Bernd Wurth, Klaus Eckl