24 search results - page 2 / 5 » An Evolvable Combinational Unit for FPGAs |
FPL
2007
Springer
13 years 11 months ago
2007
Springer
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
CODES
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. Function evaluation is at the core of many compute-intensive applications which perform well on reconfigurable platforms. Yet, in order to implement function evaluation ...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...
FPGA
2010
ACM
13 years 10 months ago
2010
ACM
This paper describes a heterogeneous computer cluster called Axel. Axel contains a collection of nodes; each node can include multiple types of accelerators such as FPGAs (Field P...