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CODES
2004
IEEE
13 years 9 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
PAMI
2010
205views more  PAMI 2010»
13 years 3 months ago
Learning a Hierarchical Deformable Template for Rapid Deformable Object Parsing
In this paper, we address the tasks of detecting, segmenting, parsing, and matching deformable objects. We use a novel probabilistic object model that we call a hierarchical defor...
Long Zhu, Yuanhao Chen, Alan L. Yuille
VEE
2010
ACM
218views Virtualization» more  VEE 2010»
14 years 8 days ago
Improving compiler-runtime separation with XIR
Intense research on virtual machines has highlighted the need for flexible software architectures that allow quick evaluation of new design and implementation techniques. The inte...
Ben Titzer, Thomas Würthinger, Doug Simon, Ma...
IPPS
2009
IEEE
13 years 12 months ago
Annotation-based empirical performance tuning using Orio
In many scientific applications, significant time is spent tuning codes for a particular highperformance architecture. Tuning approaches range from the relatively nonintrusive (...
Albert Hartono, Boyana Norris, Ponnuswamy Sadayapp...
CLUSTER
2007
IEEE
13 years 11 months ago
Balancing productivity and performance on the cell broadband engine
— The Cell Broadband Engine (BE) is a heterogeneous multicore processor, combining a general-purpose POWER architecture core with eight independent single-instructionmultiple-dat...
Sadaf R. Alam, Jeremy S. Meredith, Jeffrey S. Vett...