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» An FPGA architecture for DRAM-based systolic computations
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FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 9 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ASAP
2008
IEEE
186views Hardware» more  ASAP 2008»
13 years 11 months ago
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-thro...
Arpith C. Jacob, Jeremy Buhler, Roger D. Chamberla...
RECONFIG
2008
IEEE
184views VLSI» more  RECONFIG 2008»
13 years 11 months ago
FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m)
This paper describes an efficient arithmetic processor for elliptic curve cryptography. The proposed processor consists of special architectural components, the most important of...
Ilker Yavuz, Siddika Berna Ors Yalcin, Çeti...
WOB
2004
120views Bioinformatics» more  WOB 2004»
13 years 6 months ago
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming
ABSTRACT. Reconfigurable systolic arrays can be adapted to efficiently resolve a wide spectrum of computational problems; parallelism is naturally explored in systolic arrays and r...
Ricardo P. Jacobi, Mauricio Ayala-Rincón, L...
IPPS
2009
IEEE
13 years 11 months ago
Accelerating HMMer on FPGAs using systolic array based architecture
HMMer is a widely-used bioinformatics software package that uses profile HMMs (Hidden Markov Models) to model the primary structure consensus of a family of protein or nucleic aci...
Yanteng Sun, Peng Li, Guochang Gu, Yuan Wen, Yuan ...