11 search results - page 2 / 3 » An FPGA architecture for DRAM-based systolic computations |
DSD
2009
IEEE
13 years 9 months ago
2009
IEEE
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computat...
ASAP
2007
IEEE
13 years 11 months ago
2007
IEEE
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
IPPS
2003
IEEE
13 years 10 months ago
2003
IEEE
This work presents the architecture of PROSIDIS, a special purpose processor designed to search for the occurrence of substrings similar to a given ‘template string’ within a ...
ASAP
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
DATE
2009
IEEE
14 years 6 hour ago
2009
IEEE
Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. For the recently available high definition frame sizes and hi...