25 search results - page 3 / 5 » An FPGA design of AES encryption circuit with 128-bit keys |
AFRICACRYPT
2008
Springer
13 years 11 months ago
2008
Springer
Rijndael is a block cipher designed by V. Rijmen and J. Daemen and it was chosen in its 128-bit block version as AES by the NIST in October 2000. Three key lengths - 128, 192 or 25...
JUCS
2007
13 years 5 months ago
2007
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
TII
2010
13 years 1 days ago
2010
Software intellectual property (SWIP) is a critical component of increasingly complex field programmable gate arrays (FPGA)-based system-on-chip (SOC) designs. As a result, develop...
TC
2010
13 years 1 days ago
2010
Tweakable enciphering schemes are length preserving block cipher modes of operation that provide a strong pseudo-random permutation. It has been suggested that these schemes can b...
CHES
2005
Springer
13 years 11 months ago
2005
Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...