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» An FPGA design of AES encryption circuit with 128-bit keys
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ISSA
2004
13 years 6 months ago
High Data Rate 8-Bit Crypto Processor
This paper describes a high data rate 8-bit Crypto Processor based on Advanced Encryption Standard (Rijndael algorithm). Though the algorithm requires 32-bit wide data path but ou...
Sheikh Muhammad Farhan
CHES
2007
Springer
154views Cryptology» more  CHES 2007»
13 years 11 months ago
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
Abstract. This paper presents a design-space exploration of the Galois/Counter Mode (GCM) algorithm with Advanced Encryption Standard (AES) as underlying block cipher for high thro...
Stefan Lemsitzer, Johannes Wolkerstorfer, Norbert ...
FCCM
1998
IEEE
113views VLSI» more  FCCM 1998»
13 years 9 months ago
PAM-Blox: High Performance FPGA Design for Adaptive Computing
PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High- performance FPGA design for adaptive computing is simplified by using a ...
Oskar Mencer, Martin Morf, Michael J. Flynn
DAC
2007
ACM
13 years 8 months ago
Side-Channel Attack Pitfalls
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
Kris Tiri
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 6 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...