67 search results - page 2 / 14 » An IDDQ Sensor for Concurrent Timing Error Detection |
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
DFT
2008
IEEE
13 years 7 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
: Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concu...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
SUTC
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— Sensor networks are being increasingly deployed for collecting critical data in various applications. Once deployed, a sensor network may experience faults at the indiv...